Senior Embedded Software Engineer – Defence System

This role, based onsite in Navi Mumbai, India, positions you as a critical bridge between hardware and software. You will be responsible for ingesting high-throughput data from sensors (SDR receivers, radar modules, spectrum analyzers, cameras) into ruggedized Single Board Computers (SBCs), processing it using multi-threaded and multi-core architectures with hardware accelerators, and transmitting the processed outputs to external systems via both open-standard and proprietary communication protocols.

This position requires deep expertise in low-level C/C++ systems programming, real-time data pipeline design, hardware peripheral integration, and performance optimization on resource-constrained embedded platforms used in mission-critical defence applications.

As a Senior Embedded Software Engineer – Defence System, your responsibilities would typically be to:

• Design and develop high-performance C/C++ applications on ruggedized SBC platforms (e.g., COM Express, VPX/VME, SMARC, custom MIL-grade boards) running Linux and/or RTOS environments.

• Architect and implement multi-threaded, multi-core data processing pipelines that ingest high-bandwidth sensor data (USB 3.0/3.1 at 5–10 Gbps, PCIe, Ethernet, serial interfaces) from SDR receivers, radar front-ends, spectrum analyzers (such as Aaronia SPECTRAN V6), and camera feeds.

•  Integrate and orchestrate hardware accelerators for parallel compute workloads — including but not limited to NVIDIA Jetson (CUDA/TensorRT), Intel Movidius/OpenVINO, Hailo AI processors, Xilinx/AMD Zynq FPGAs, TI C66x/C71x DSP platforms, and other vendor-specific acceleration hardware — selecting the right accelerator based on latency, throughput, power, and thermal constraints.

• Develop device drivers, kernel modules, and Board Support Packages (BSPs) to interface SBC platforms with peripheral hardware including SDRs, radar modules, GPIO, SPI, I2C, UART, and high-speed USB endpoints.

• Build efficient data pipelines that process temporal/time-series data streams (IQ samples, radar returns, spectral data, video frames) with real-time constraints, applying techniques such as ring buffers, lock-free queues, DMA transfers, zero-copy I/O, and scatter-gather operations.

•  Push processed data to external systems (command & control consoles, HPC clusters, recording servers, display systems) using open-standard protocols (DDS/RTPS, MQTT, ZeroMQ, gRPC, REST, VITA 49 Radio Transport) and proprietary/military communication standards (MIL-STD-1553, STANAG, Link 16).

•  Implement and adhere to defence interoperability standards including OpenVPX (VITA 65), SOSA (Sensor Open Systems Architecture), CMOSS, and GVA/NGVA where applicable.

• Optimize CPU/memory/IO utilization through profiling, NUMA-aware allocation, CPU pinning, real-time scheduling (PREEMPT_RT, Xenomai), cache optimization, and interrupt affinity tuning for deterministic, predictable performance under sustained loads.

• Collaborate closely with RF engineers, FPGA teams, and systems integration engineers at the site to ensure seamless hardware-software co-design across the full signal chain from antenna to display.

• Maintain comprehensive technical documentation including Interface Control Documents (ICDs), Software Design Descriptions (SDDs), and API specifications compliant with defence documentation standards (JSS 55555, MIL-STD-498).